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AR# 60489

Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier: GTH/GTP Production RX reset sequence can get stuck

Description

All of the RX modules in the wizard for GTPE2 + GTHE2 execute a series of DRP operations as per the 7 Series GTH and GTP Production RX reset sequence requirements covered in (Xilinx Answer 53779) and (Xilinx Answer 53561).
 
These operations are:

(a) Read the DRP value for the internal data width
(b) Write a DRP value (Force to 16-bit internal data width)
(c) Write the DRP value read in (a) to restore the original internal data width
 
If the module receives another reset from the user after (b) but before (c) then on the next iteration it will read a 16-bit internal data width in step (a), and thus at the end of the sequence will restore a 16-bit internal data width.

This means that the transceiver is now permanently in 16-bit mode and the only way to recover is to re-program the device.

Solution

This issue is fixed in the wizard version v3.3 in Vivado 2014.2.
 
For wizard versions v3.2 or earlier, the workaround is as follows.

An example RX sequence module file is attached to this answer record.

 

1.  Add the logic below in the RX sequence modules.
 
reg flag =1'b0;
reg [15:0] original_rd_data;
always @ (posedge DRPCLK)
begin
if( state == wr_16 || state == wait_pmareset || state == wr_20 || state == wait_wr_done1)
           flag <= 1'b1;
else if(state == wait_wr_done2)
           flag <= 1'b0;
end
always @ (posedge DRPCLK)
begin
if( state == wait_rd_data && DRPRDY == 1'b1 && flag == 1'b0)
            original_rd_data <= DRPDO;
end
 
2. Add flag and original_rd_data to the sensitivity list.

Enter this logic:
 

always @ (DRPRDY or state or rd_data or DRPDO or gtrxreset_ss or flag or original_rd_data) begin

 
in place of
 

always @ (DRPRDY or state or rd_data or DRPDO or gtrxreset_ss) begin


3. Replace the logic of the wait_rd_data state

Enter this logic:
 
wait_rd_data : begin
                                gtrxreset_i = 1'b1;
                if (DRPRDY && !flag) begin
                                next_rd_data = DRPDO;
               end
               else if (DRPRDY && flag) begin
                               next_rd_data = original_rd_data;
               end
               else  begin 
                              next_rd_data = rd_data;
               end
               end
 
in place of :
 
wait_rd_data : begin 
                                 gtrxreset_i = 1'b1;
                if (DRPRDY)
                                next_rd_data = DRPDO;
                else
                                next_rd_data = rd_data;
                end

Affected IP's:

Please refer to these IP answer records for more information on respective IP's that are impacted.

1000BASE-X/SGMII and QSGMII: (Xilinx Answer 60784)
JESD204: (Xilinx Answer 60707)
Aurora 8B10B: (Xilinx Answer 60836)
DisplayPort: (Xilinx Answer 61799)

Revision History
08/15/2014 - Added AR for DisplayPort
06/23/2014 - Added AR for Aurora 8B10B

05/22/2014 - Initial release



Attachments

Associated Attachments

Name File Size File Type
gtp_gtrxreset_seq.v 6 KB V

Linked Answer Records

Associated Answer Records

AR# 60489
Date Created 05/01/2014
Last Updated 08/22/2014
Status Active
Type Design Advisory
Devices
  • Artix-7
  • Virtex-7
  • Virtex-7 HT
  • Zynq-7000
IP
  • 7 Series FPGAs Transceivers Wizard