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AR# 60531

2014.1 Vivado IP Flows - Error [Vivado 12-3346] will be reported during opt_design, for the GTZ example design generated in 7 Series FPGAs Transceivers Wizard


Generating the GTZ example design in the 7 Series FPGAs Transceivers Wizard returns the following error message:

[Vivado 12-3346] Could not set property 'LOCK_PINS' on instance caui_1_serdes_init_i/caui_1_serdes_i/inst/octal0_caui_1_serdes_i/gtze2_inf_north/RXHEADER37_LUT1A.
The cell is placed at site SLICE_X181Y412. The cell already has a 'LOCK_PINS' property.
Please unplace the cell and reset the property prior to applying a new value.

The implementation flow will continue in spite of the error.

Can this error message be ignored safely?


Before the opt_design step, v7ht.tcl is sourced twice.

This error is caused by the LOCK_PINS contained in v7ht.tcl being executed twice.

Because the LOCK_PINS property is set correctly, the error message can be ignored safely.

The issue where v7ht.tcl is read twice is fixed in Vivado 2014.2.

AR# 60531
Date Created 05/05/2014
Last Updated 01/14/2015
Status Active
Type Known Issues
  • Virtex-7
  • 7 Series FPGAs Transceivers Wizard