UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60549

Known Ultrascale SelectIO issues in Vivado 2014.1 - Known Issues Article

Description

Known Ultrascale SelectIO issues in Vivado 2014.1.  

This is a known issues article for the Ultrascale SelectIO when using Vivado version 2014.1.

Solution

1) Automatic pin location placement can cause compatible IO standards to be incorrectly flagged by DRC as illegally having different VCCO levels into the same mini-bank:

For some designs, Vivado's placement algorithm is failing to analyze the IOSTANDARD attribute for automatically placed pins. 
Instead, it can ignore an assigned standard and assume that a default standard is used (LVCMOS18). 
Because the assigned IOSTANDARD attribute is ignored, the automatically placed pins may flag errors as being incompatible.
For example, if  OUTPUT_PIN1 and OUTPUT_PIN2 are assigned an IOSTANDARD of HSTL_I in the XDC but no LOC is assigned, the pins may get placed legally in the same bank, but the following DRC may be flagged:
ERROR: [Drc 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 18. For example, the following two ports in this bank have conflicting VCCOs: 
OUTPUT_PIN1 (HSTL_I, requiring VCCO=1.500) and OUTPUT_PIN2 (LVCMOS18, requiring VCCO=1.800)
Work-around: Use the Vivado Pin Planning tool, or placement attributes (in the XDC file)  to manually place all I/O ports in the design.
 
2) Ultrascale does not support VCCAUX_IO:

Xilinx's 7 Series and Zynq 7000 FPGA's supported two VCCAUX_IO voltage levels: 1.8V and 2.0V. 
Users would indicate which board voltage level was used by assigning the attribute VCCAUX_IO to NORMAL (1.8V), HIGH (2.0V), or DONTCARE. 
The attributes could be assigned within the RTL source code, or as a property in an XDC file.  The Ultrascale family does not support multiple VCCAUX_IO voltage levels, and therefore there is no need or use for supporting this attribute in an Ultrascale design. 
Vivado 2014.1 does not flag any DRC warning or error if the attribute is used in an Ultrascale design, but this will eventually become a CRITICAL WARNING.

Work-around
: Remove all instances of the VCCAUX_IO attribute from an Ultrascale design.
 
3) Automatic placement is illegally placing input with ODT = RTT_240 into a HR bank:

Similar to Xilinx's 7 Series family, the Ultrascale family has both High Performance (HP), and High Range (HR) I/O banks. 
New to Ultrascale, on-die input termination for an IO standard is determined via a new constraint, "ODT" (acronym for "On-Die Termination").
Although this feature is supported in both HP and HR I/O banks, ODT value of RTT_240 and RTT_120  is only supported in HP I/O banks
.

Vivado 2014.1 has a bug in the automatic placement algorithm that can cause I/Os with the ODT attribute set to RTT_240 to be placed in an HR I/O bank.  This will result in a DRC ERROR. For example:
ERROR: [Drc 23-20] Rule violation (PORTPROP-11) Attribute value compatibility with bank type - Port data_in_p[0] has property ODT set to RTT_240, but this value is not compatible with the bank type the port is placed in (High Range).
Work-around: Use the Vivado Pin Planning tool or placement attributes (in the XDC file) to manually place all I/O ports in the design. 
Do not assign any I/O standards with ODT attribute 
set to RTT_240 or RTT_120 for I/O pins that are placed in HR I/O banks.

4) Bitgen error when IBUFDS primitive with DIFF_TERM=TRUE and IOSTANDARD=SLVS_400_25 is assigned in an HR I/O Bank: 

Vivado 2014.1 is not supporting the combination of an IBUFDS (differential input buffer), when the I/O standard is SLVS_400_25, and the internal differential termination resistor is turned on (DIFF_TERM= TRUE). 
If a design has this combination on one or more I/O pins, bitgen will fail with an ERROR. 

Work-around: There is no work-around at this time.

5) HSUL_12_DCI and DIFF_HSUL_12_DCI have the ODT attribute default to "RTT_120" for Kintex and Virtex UltraScale in Vivado 2014.1.

The UltraScale family should default to having ODT turned off (RTT_NONE) for the HSUL_12_DCI and DIFF_HSUL_12_DCI I/O standards. 
However, in the Vivado 2014.1 release it defaults to RTT_120. 
Further, it cannot be set to RTT_NONE. 
These issues will be fixed in the 2014.2 software release to default to having the ODT attribute set to RTT_NONE. 
If an I/O is behaving as if a pull-up is enabled when the design is intended to have ODT=RTT_NONE, it is likely due to this issue, and you should use the following work-around:

Work-around: Change the HSUL I/O standards to the non-DCI versions in the design file, wherever the I/O standard was specified - either in the Pin Planning GUI, source RTL code, or the XDC file. 
For example, replace HSUL_12_DCI with HSUL_12, and replace DIFF_HSUL_12_DCI with DIFF_HSUL_12.
 
AR# 60549
Date Created 05/07/2014
Last Updated 05/12/2014
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.1