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AR# 60570

7-Series Integrated Block for PCI Express v3.0(Rev2) - Example design Root Port model does not accept Non-Posted transactions


Version Found: v3.0 (Rev2)
Version Resolved and other Known Issues: See (Xilinx Answer 54643)

When sending non-posted transactions to the example design Root Port model in simulation, the packets never arrive.

The Root Port seems to drop the packet.


This is a known issue to be fixed in a future release of the core. 

To work around this issue in the current release, make the following modification in  project/pcie_7x_0_example/pcie_7x_0_example.srcs/sim_1/imports/pcie_7x_0/simulation/dsport/xilinx_pcie_2_1_rport.7x.v :


.rx_np_ok       (~trn_rnp_ok_n),

.rx_np_req      (1'b0),


.rx_np_ok       (1'b1),

.rx_np_req      (1'b1),

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
07/31/2014 - Initial Release 

AR# 60570
Date Created 05/08/2014
Last Updated 07/31/2014
Status Active
Type General Article
  • 7 Series Integrated Block for PCI Express (PCIe)