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AR# 60585

Vivado IP Integrator - CRITICAL WARNING: [BD 41-1347] [BD 41-1343] Reset pin M02_ARESETN is connected to asynchronous reset source FCLK_RESET0_N.


Critical Warnings similar to the following are received during design validation in Vivado 2014.1.
CRITICAL WARNING: [BD 41-1347] Reset pin /axi_mem_intercon/M02_ARESETN (associated clock /axi_mem_intercon/M02_ACLK) is connected to asynchronous reset source /processing_system7_0/FCLK_RESET0_N.
This may prevent design from meeting timing. Instead, it should be connected to reset source /rst_processing_system7_0_50M/peripheral_aresetn.
CRITICAL WARNING: [BD 41-1343] Reset pin /axi_mem_intercon/S00_ARESETN (associated clock /axi_mem_intercon/S00_ACLK) is connected to reset source /rst_clk_wiz_1_100M/peripheral_aresetn (synchronous to clock source /clk_wiz_1/clk_out1).
This may prevent design from meeting timing. Please add proc_sys_reset module to create a reset, that is synchronous to the associated clock source /clk_wiz_1/clk_out2.
These warnings were not received in Vivado 2013.4.


This is a new function added in 2014.1 to indicate the reset connection.
From axi-interconnect v2.0, the aresetn input must be synchronized to the corresponding aclk (refer to pg059 for more information).
In the previous versions of Vivado, this was not checked.
If you have different frequency of clocks, but they are all synchronized, this Critical Warning can be ignored.

Otherwise you need to use the separate proc_sys_reset module to synchronize the reset to the clock.

If your design uses a custom IP in IPI, you can apply an ASSOCIATED_RESET property to your IP to resolve the Critical Warnings:

  1. Right-click on your custom IP block in the IPI design, and select "Edit in IP Packager".
  2. Once the design is open, go to the "Ports and Interfaces" section, and expand "Clock and Reset Signals".
  3. Right-click the clock interface you wish the resets to be associated with, and select "Edit Interface".
  4. Go to the Parameters tab and click on the plus (+) to add a parameter.
  5. Enter "ASSOCIATED_RESET" for the name, and you should get a new row.
  6. In the Value column, add the required reset ports.
    Generally the ports listed in the Critical Warning are used.
    To list multiple ports, use a colon to separate the names, portname1:portname2:etc.
  7. Click OK, then go to the "Review and Package" section and click "Re-Package IP".
  8. Back in your original IPI design, this block will be updated automatically.
    Once updated, you can click on "Validate Design" to verify that the Critical Warnings no longer occur.
AR# 60585
Date 03/05/2015
Status Active
Type General Article
  • Zynq-7000
  • Kintex-7
  • Artix-7
  • Virtex-7
  • Vivado Design Suite - 2014.1
  • AXI Interconnect
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