Critical Warnings similar to the following are received during design validation in Vivado 2014.1.
CRITICAL WARNING: [BD 41-1347] Reset pin /axi_mem_intercon/M02_ARESETN (associated clock /axi_mem_intercon/M02_ACLK) is connected to asynchronous reset source /processing_system7_0/FCLK_RESET0_N.
This may prevent design from meeting timing. Instead, it should be connected to reset source /rst_processing_system7_0_50M/peripheral_aresetn.
CRITICAL WARNING: [BD 41-1343] Reset pin /axi_mem_intercon/S00_ARESETN (associated clock /axi_mem_intercon/S00_ACLK) is connected to reset source /rst_clk_wiz_1_100M/peripheral_aresetn (synchronous to clock source /clk_wiz_1/clk_out1).
This may prevent design from meeting timing. Please add proc_sys_reset module to create a reset, that is synchronous to the associated clock source /clk_wiz_1/clk_out2.