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AR# 60591

2013.4 Vivado Implementation - False LUTLP-1 Critical Warning for path through LUT6_2


Vivado DRC reports a false positive for a combinational loop for a path that does loop back to the input of the LUT complex, but to an input pin that is not used by the LUT driving the circuit.

LUTLP-1#1 Critical Warning
Combinatorial Loop  
2 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. To allow bitstream creation for designs with combinatorial logic loops (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. U_rtesi_fpga/U_rtesi_20g_dp0/U_esi4_top_local/esi4_rx_channel_inst/disp_sh_2nd_srdy_nxt_ss0_lut6_2/LUT5 (in U_rtesi_fpga/U_rtesi_20g_dp0/U_esi4_top_local/esi4_rx_channel_inst/disp_sh_2nd_srdy_nxt_ss0_lut6_2 macro), U_rtesi_fpga/U_rtesi_20g_dp0/U_esi4_top_local/esi4_rx_channel_inst/disp_sh_2nd_srdy_nxt_1_sqmuxa_6.
Related violations: <none>


A CR has been filed and this issue is scheduled to be fixed in a future release.

To work around this issue, the Critical Warning can be downgraded.

After examination to determine that it is not a true combinational loop, use the command below:

set_property SEVERITY {Warning} [get_drc_checks LUTLP-1] 
AR# 60591
Date 05/16/2014
Status Active
Type General Article
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2013.4