We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60610

2014.1 Artix-7 Place - Clock Placer incorrectly rejects valid clock configuration involving reference clock driving to adjacent quads


A design with a valid clock configuration fails with the following clock placement error:

[Place 30-512] Clock region assignment has failed. Clock buffer 'gtwizard_0_support_i/gt_usrclk_source/ibufds_instq1_clk0' (IBUFDS_GTE2) is placed at site IBUFDS_GTE2_X1Y0 in CLOCKREGION_X1Y0. Its loads need to be placed in the area enclosed by clock regions CLOCKREGION_X1Y0 and CLOCKREGION_X1Y0. One of its loads 'gtwizard_0_support_i/common0_i/gtpe2_common_i' (GTPE2_COMMON) is placed in site GTPE2_COMMON_X0Y0 in CLOCKREGION_X0Y0 which is outside the permissible area.


This problem will be fixed in the 2014.2 release of Vivado Design Suite so that the design will implement successfully.
AR# 60610
Date Created 05/12/2014
Last Updated 05/19/2014
Status Active
Type General Article
  • Artix-7
  • Vivado Design Suite - 2014.1