We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60625

2014.2 AXI_Chip2Chip - [IP_​Flow 19-3458] Validation failed for parameter 'ID Width(C_​AXI_​ID_​WIDTH)' for BD Cell '/​axi_​chip2chip_​0'. Value '13' is out of the range (1,​6)


The current set up of having an AXI Chip2Chip with >6 bits is resulting in errors in Vivado. 

Why is this happening?


Having an Axi chip2chip with >6 bits is currently not supported.

It is planned to be supported in Vivado 2014.3.

If this set up is being used with a Zynq-7000 PS M_AXI_GP interface, consider setting the ID Remap option.

This will reduce the PS ID width from 12-bits to 6-bits, potentially avoiding this limitation.

AR# 60625
Date 11/13/2017
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2014.1
  • AXI Interconnect
  • AXI Chip2Chip
Boards & Kits
  • Zynq-7000 SoC ZC706 Evaluation Kit
Page Bookmarked