The current setup of having an AXI Chip2Chip with >6 bits is resulting in errors in Vivado.
Why is this happening?
Having an Axi chip2chip with >6 bits is currently not supported.
It is planned to be supported in Vivado 2014.3.
If this setup is being used with a Zynq-7000 PS M_AXI_GP interface, consider setting the ID Remap option.
This will reduce the PS ID width from 12-bits to 6-bits, potentially avoiding this limitation.
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