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AR# 60712

LogiCORE IP G.709 FEC Encoder/Decoder - Why do the post implementation/post synthesis simulation results vary from the behavioral simulation results in 2014.2 when VHDL is used

Description

Why do the post implementation/post synthesis simulation results of the G.709 FEC Decoder vary from the behavioral simulation results in 2014.2 when the simulation language is VHDL?

Solution

The Behavior simulation is correct. This is a known issue affecting VHDL only.
 
It is restricted to cases using the Decoder and affects only UltraScale devices.
 
The workaround is to use Verilog as the simulation language.
 

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Master Answer Records

AR# 60712
Date Created 05/19/2014
Last Updated 07/28/2014
Status Active
Type General Article
IP
  • Communication and Networking