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AR# 60714

MiG 7 Series DDR3 - When simulating DDR2 Example Designs from the Vivado GUI with Modelsim/Questasim undefined modules can be reported


When running a Modelsim or QuestaSim simulation for my DDR2 MiG example design, through the Vivado GUI using "Run Behavioral Simulation" option I receive the following errors:

 No such file or directory. (errno = ENOENT)
# ** Error: f:/ambrosef/CASE_1009057/2014_05_16/Project_files/exdes/DDR2_A7_example/DDR2_A7_example.srcs/sources_1/ip/DDR2_A7/DDR2_A7/user_design/rtl/phy/mig_7series_v2_0_ddr_calib_top.v(1303): Module 'mig_7series_v2_0_ddr_phy_wrlvl' is not defined.
# No such file or directory. (errno = ENOENT)
# ** Error: f:/ambrosef/CASE_1009057/2014_05_16/Project_files/exdes/DDR2_A7_example/DDR2_A7_example.srcs/sources_1/ip/DDR2_A7/DDR2_A7/user_design/rtl/phy/mig_7series_v2_0_ddr_calib_top.v(1325): Module 'mig_7series_v2_0_ddr_phy_ck_addr_cmd_delay' is not defined.
# Optimization failed

Why does this occur? Is it possible to work around these errors?


This issue has been seen in some configurations and can be worked around using either of the following options:

  • In the Simulation settings in the Vivado GUI, add the "-novopt" switch to the "More Vsim Options" section.
  • Alternatively, the MiG core delivers a "sim.do" file with the example design which can be run directly from the following location in the example project, <path_to_project_location>\project_name.srcs\sources_1\ip\ip_name\ip_name\example_design\sim\sim.do

Revision History
05/23/2014 - Initial Release

AR# 60714
Date Created 05/19/2014
Last Updated 06/11/2014
Status Active
Type General Article
  • Virtex-7
  • Kintex-7
  • MIG 7 Series