UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60784

Ethernet 1000BASE-X PCS/PMA or SGMII core and QSGMII core - Vivado 2014.1 and earlier - GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recover

Description

When using Ethernet 1000BASE-X PCS/PMA or SGMII core v14.2 or QSGMII core v3.2 and earlier, production reset GTP and GTH DRP sequence can end up in a hung state that requires reconfiguration to recover (Xilinx Answer 60033)

The failure is only seen when a second reset is issued to the core while a previous reset sequence is underway. 

The reset sequence is started automatically after configuration, so this could happen if the main core reset is toggled shortly after the device is configured. 

Affected core configurations that use the DRP reset logic are:

  • 1000BASE-X and SGMII 7-Series GTP and GTH
  • QSGMII 7-Series GTP

The failure happens due to a DRP register setting getting stuck with a 16/32-bit Rx data width instead of the required 20/40-bit data width. 


1000BASE-X and SGMII
use a 20-bit data width during normal operation and QSGMII uses a 40-bit data width during normal operation.

However, DRP logic sets the data width to16/32-bits during a reset sequence to avoid production reset issues (see GT Transceiver UG for more information on required reset logic).  

The failure is only seen when a second reset is issued to the core while a previous reset sequence is underway.

Solution

To work around this, the second DRP write can be changed to ensure that the data width is set back to 20 or 40 instead of relying on the initially read value which can get stuck at 16 or 32, if a reset is issued during the DRP sequence. 

The DRP update should be made to <core_name>_*_gtrxreset_seq.v/vhd (if used also change <core_name>_*_gtrxrate_seq.v/vhd and <core_name>_*_ gtrxpmarst_seq.v/vhd ) and is the same for both 20 and 40 bit data widths.


For VHDL change the following:

      --write to 20-bit mode

      WHEN wr_20 => 

        ....

        drpdi_o <= rd_data(15 downto 0); --restore user setting per prev read

To:

      --write to 20-bit mode

      WHEN wr_20 =>

        ...

         drpdi_o <= rd_data(15 downto 12) & '1' & rd_data(10 downto 0); --restore 20-bit mode


For Verilog change the following:

//write to 20-bit mode

                wr_20 : begin

                        ....

                        drpdi_o = rd_data[15:0]; //restore user setting per prev read

                end

To:

//write to 20-bit mode

                wr_20 : begin

                         ....

                        drpdi_o = {rd_data[15:12], 1'b1, rd_data[10:0]}; //restore 20-bit

                end

The GT files for these cores have been updated in 2014.2.

AR# 60784
Date Created 05/22/2014
Last Updated 08/05/2014
Status Active
Type General Article
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII
  • QSGMII