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AR# 60799

Design Assistant for Vivado Synthesis - Help with Synthesis HDL Attribute Support - fsm_encoding, fsm_safe_state, srl_style


This answer record describes the Vivado Synthesis Attributes fsm_encoding, fsm_safe_state, srl_style, and also provides coding examples for them.
The coding examples are attached to this answer record.

The answer record also contains information related to known issues and good coding practices.

: Each coding example can be used to directly create a Vivado project.
Please refer to the header in each source file for the Synthesis attributes covered in each example.



The fsm_encoding attribute directs Vivado Synthesis on what encoding style is to be used with a finite state machine.
The value of "auto" is the default and allows Vivado Synthesis to choose the best FSM encoding based on the coding style.
An FSM must first be inferred for the fsm_encoding to be used.

Acceptable values for this are: one_hot, sequential, johnson, gray, none and auto.

Verilog Example:

(* fsm_encoding = "gray" *)reg [2:0] state;

VHDL Example:

attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "gray";



Applying the "fsm_safe_state" attribute will direct Vivado Synthesis to insert logic into a state machine that specifies what should happen in the case of an illegal state.

An FSM that is in an illegal state can cause unpredictable output, which can be avoided by the safe state.

Acceptable values are: auto_safe_state, reset_state, power_on_state, default_state

  • auto_safe_state: Uses Hamming-3 encoding for auto-correction for one bit/flip.
  •  reset_state: Forces the state machine into the reset state using Hamming-2 encoding detection for one bit/flip.

Setting the fsm_safe_state to a value of "reset_state" will have the encoded state machine use a reset condition in the case where an invalid state is found.

A reset condition would be any state assignment to a state assignment on reset. Below is an example:

   if (reset ='1') then
    state <= s1;

  • "power_on_state" Forces the state machine into the power-on state using Hamming-2 encoding detection for one bit/flip.

The "power_on_state" value for the fsm_safe_state attribute will have the same functionality as the "reset_state".

This can be used in cases where there is no reset condition defined in the RTL and the intention is to use the initial INIT values of the state registers as a safe state.

  • "default_state" Forces the state machine into the state that is specified with the default state in RTL, even if that state is unreachable, using Hamming-2 encoding detection for one bit/flip.

For Verilog, the "default" keyword can be used along with the fsm_safe_state attribute to specify that the default value should be used for the safe state.

For VHDL, the "when others" keywords has the same effect. 

With the default_state set for the fsm_safe_state attribute, the value applied to the state register in the default or "when others" section of a case statement will be used as the safe state.

Verilog Example:

(* fsm_safe_state = "reset_state" *) reg [2:0] state;

VHDL Example:

attribute fsm_safe_state : string;
attribute fsm_safe_state of state : signal is "reset_state";


The srl_style attribute directs Vivado Synthesis on whether an SRL primitive should be inferred, and if a register is to be placed before the SRL, after the SRL, or both. 

For example, setting the srl_style attribute to a value of "reg_srl", will infer an SRL with a register driving the input of the SRL.

Acceptable Values are: register, srl, srl_reg, reg_srl, reg_srl_reg

Verilog Example:

(* srl_style = "srl_reg"*) reg [clock_cycles-1:0] shift_reg = {clock_cycles{1'b0}};

VHDL Example:

attribute srl_style : string;
attribute srl_style of shift_reg : signal is "srl_reg";

Please refer to the following and (UG901) for any additional details on the acceptable values for fsm_safe_state & srl_style attributes:

Attribute NameHDL Files
  • fsm_encoding.v
  • fsm_encoding.vhd
  • fsm_safe_state.v
  • fsm_safe_state.vhd
  • srl_style.v
  • srl_style.vhd


Associated Attachments

Name File Size File Type
fsm_encoding.zip 1 KB ZIP
fsm_safe_state.zip 1 KB ZIP
srl_style.zip 1 KB ZIP
AR# 60799
Date 10/23/2017
Status Active
Type Solution Center
  • Vivado Design Suite
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