Version Found: MIG v5.0
Version Resolved: See (Xilinx Answer 58435)
When simulating the MIG UltraScale DDR4 core with the encrypted DDR4 Micron model, the model is not latching the write data on the current cycle but rather on the next CK cycle.
This causes the data to be written on the wrong cycle and as a result read data errors are seen in simulation.
Specifically, Xs will be seen at the end of the read.
This has been seen on all MIG supported simulators.
sys_clk_i = #(14045/2.0) ~sys_clk_i;The input clock for this design is 14045. This should be modified according to the value used during MIG core generation.
wire [31:0] c0_ddr4_app_wdf_mask;
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