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AR# 60832

Aurora 8B10B v10.2 - Ultrascale - Hold violations with some core configurations

Description

Some of the Aurora 8B10B example design implementations fail when run on UltraScale devices with the following critical warning:

CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.


This Answer record provides the edits required to resolve the timing issues.

Solution

1. Open the <component_name>_exdes.v file and add Xilinx BUFG primitives to the INIT_CLK_IN clock input pin as given below.

BUFG init_clk_bufg

   (

      .I     (INIT_CLK_IN)

      .O   (init_clk_i),

   );

 2. Change the init_clk_in port connection on the aurora_module_i instantiation in the <component_name>_exdes.v file.

From:

. init_clk_in(INIT_CLK_IN),

To:

.init_clk_in(init_clk_i),

Save the file and run implementation. 

Revision History:

5/27/2014 - Initial release

AR# 60832
Date Created 05/26/2014
Last Updated 06/23/2014
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.1
IP
  • Aurora 8B/10B