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AR# 60833

Aurora 64B66B v9.2 - Ultrascale - Hold violations with some core configurations

Description

Some of the Aurora 64B66B example design implementations fail when run on UltraScale devices with the following critical warning:

CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

This Answer record provides the edits required to resolve the timing issues.

Solution

1. Open the <component_name>_exdes.v file. 

Remove the following assignment

assign INIT_CLK_i = init_clk;

2. Add Xilinx BUFG primitives to the INIT_CLK_IN clock input pin as given below.

BUFG initclk_bufg_i

     (

         .I  (init_clk),

         .O  (INIT_CLK_i)

     );

3. Change the init_clk_in port connection on the <component_name>_block_i instantiation in the <component_name>_exdes.v file

From:

         .init_clk                              (init_clk),

To:

         .init_clk                              (INIT_CLK_i),


Save the file and run implementation.


Revision History:

06/23/2014 - Initial release

AR# 60833
Date Created 05/27/2014
Last Updated 06/23/2014
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.1
IP
  • Aurora 64B/66B