We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60844

2014.1 Vivado IPI - How can I split and merge a bus in IPI?


I have an n-bit signal output from one of the IP blocks that I want to split in order to assign each bit to an input on different downstream IPs.

Is there a split block or another option available in IPI to do this?

Additionally, Is it possible to insert bits into a bus (like input to the GPIO block)?


To split a bus, you can use a "slice" IP.

This IP allows slicing out one individual bit or a number of bits from a bit-vector (or bus).

The "Din Width" value specifies the input bus width.

The "Din From" and "Din To" parameters can be configured either as individual bits or bit-vectors.

In cases where individual bits are being ripped then these fields will have a value of "0" and "0" respectively to signify bit 0 of the bus, or "1" and "1" to signify bit 1 of the bus.

Typically, multiple slice IP need to be used to slice out individual bits or bit-vectors.

To insert bits into an input bus, you can use the concatenation IP instead.


AR# 60844
Date Created 05/27/2014
Last Updated 09/05/2014
Status Active
Type General Article
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2014.1