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AR# 60845

Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation


Version Found: MIG 7 Series v2.0 Rev2
Version Resolved: See (Xilinx Answer 54025)

For MIG 7 Series v2.0 Rev2 RLDRAM3 designs the SIM_BYPASS_INIT_CAL parameter is always set to "FAST" in both <core_name>_mig.v and <core_name>_mig_sim.v by default.

"FAST" should only be used for behavioral simulations and will cause calibration and data failures in hardware.

For synthesis, implementation, and hardware testing SIM_BYPASS_INIT_CAL should be set to "NONE".

This issue affects RLDRAM3 designs only.


To work around this issue you must modify the top-level parameter SIM_BYPASS_INIT_CAL inside "<core_name>_mig.v" to the following:


Revision History

06/09/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 60845
Date Created 05/27/2014
Last Updated 06/11/2014
Status Active
Type Design Advisory
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2014.1
  • MIG 7 Series