Version Found: v2.1
Version Resolved: See (Xilinx Answer 54025)
For multi-controller MIG 7 Series designs where at least one controller has an input clock period set to 5000 ps (200 MHz), the Reference Clock option can be set to the "Use System Clock" setting.
When this is set, the MIG rtl should connect the reference clock signal "clk_ref_in" to the 200 MHz input clock.
However, in the generated user design rtl top file (<module name>_mig and <module name>_mig_sim modules), the clk_ref_in is set to the input clock for the last configured controller within the MIG tool.
This means that if three controllers are generated, C0, C1, and C2, the rtl will always connect C2's input clock to clk_ref_in regardless of which controller has the 200MHz input clock.
This connection may result in the IDELAYCTRL not being clocked at the appropriate frequency and may result in timing violations.