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AR# 60860

7 Series FPGAs Transceiver Wizard v3.3 - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues for the 7 series FPGAs Transceiver Wizard v3.3 released with the Vivado 2014.2 design tool.

Solution

Known Issues and Release Notes




Issue 1:

Description: When the Vivado lab tools option is enabled in the GUI and an example design is generated, the design fails to synthesize and Returns the following:

ERROR IP vio_0.xci' is locked, its synthesis output product is in the reset state and cannot be generated. Therefore, no out-of-context (OOC) run will be created. Please select 'Report IP Status' from 'Tools/Report' or run Tcl command 'report_ip_status' for more information.


Workaround:

Please upgrade the ILA and VIO XCIs generated in the example design using the following commands.

upgrade_ip -vlnv xilinx.com:ip:vio:3.0 [get_ips  vio_0]
upgrade_ip -vlnv xilinx.com:ip:ila:4.0 [get_ips  ila_1]
upgrade_ip -vlnv xilinx.com:ip:ila:4.0 [get_ips  ila_0]

To Be Fixed: 2014.3
CR: 799843 



Issue 2:

Description:  RESETDONE will not be seen when the reference clock frequency is less than the DRP clock frequency as the synchronizer misses the CPLLRESET pulse.

Workaround:

Replace the below logic in the <component_name>_gt file:

always @(posedge gtrefclk0_in)
begin
  cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
  cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end

assign cpllpd_ovrd_i = cpllpd_wait[95];
assign cpllreset_ovrd_i = cpllreset_wait[127];

assign cpll_pd_i = cpllpd_ovrd_i;

  <component_name>_sync_block sync_cpllreset
        (
           .clk             (gtrefclk0_in),
           .data_in         (cpllreset_in),
           .data_out        (cpllreset_sync)
        );

assign cpll_reset_i = cpllreset_sync || cpllreset_ovrd_i;


With


wire    ack_i;
reg     flag = 1'b0;
reg     flag2 = 1'b0;
reg     ack_flag = 1'b0;
  // Internal Signals
  wire data_sync1;
  wire data_sync2;
  wire data_sync3;
  wire data_sync4;
  wire data_sync5;
  wire data_sync6;
  wire ack_sync1;
  wire ack_sync2;
  wire ack_sync3;
  wire ack_sync4;
  wire ack_sync5;
  wire ack_sync6;

always @(posedge gtrefclk0_in)
begin
  cpllpd_wait <= {cpllpd_wait[94:0], 1'b0};
  cpllreset_wait <= {cpllreset_wait[126:0], 1'b0};
end

assign cpllpd_ovrd_i = cpllpd_wait[95];
assign cpllreset_ovrd_i = cpllreset_wait[127];

assign cpll_pd_i = cpllpd_ovrd_i;


always @(posedge drpclk_in)
begin
if(cpllreset_in == 1'b1 && ack_flag == 1'b0)
begin
    flag <= !flag;
    flag2 <= 1'b1;
end
else
begin
    flag <= flag; 
    flag2 <= 1'b0;
end
end


always @(posedge drpclk_in)
begin
if(flag2 == 1'b1)
ack_flag <= 1'b1;
else if(ack_i == 1'b1)
ack_flag <= 1'b0;
end



  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
    .INIT (1'b0)
  ) data_sync_reg1 (
    .C  (gtrefclk0_in),
    .D  (flag),
    .Q  (data_sync1)
  );


  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
   .INIT (1'b0)
  ) data_sync_reg2 (
  .C  (gtrefclk0_in),
  .D  (data_sync1),
  .Q  (data_sync2)
  );


  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
   .INIT (1'b0)
  ) data_sync_reg3 (
  .C  (gtrefclk0_in),
  .D  (data_sync2),
  .Q  (data_sync3)
  );

  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
   .INIT (1'b0)
  ) data_sync_reg4 (
  .C  (gtrefclk0_in),
  .D  (data_sync3),
  .Q  (data_sync4)
  );

  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
   .INIT (1'b0)
  ) data_sync_reg5 (
  .C  (gtrefclk0_in),
  .D  (data_sync4),
  .Q  (data_sync5)
  );

  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
   .INIT (1'b0)
  ) data_sync_reg6 (
  .C  (gtrefclk0_in),
  .D  (data_sync5),
  .Q  (data_sync6)
  );

assign cpllreset_sync = data_sync5 ^ data_sync6;

  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
 FD #(
   .INIT (1'b0)
  ) ack_sync_reg1 (
  .C  (drpclk_in),
  .D  (data_sync6),
  .Q  (ack_sync1)
  );

  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
   .INIT (1'b0)
  ) ack_sync_reg2 (
  .C  (drpclk_in),
  .D  (ack_sync1),
  .Q  (ack_sync2)
 );

  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
   .INIT (1'b0)
  ) ack_sync_reg3 (
  .C  (drpclk_in),
  .D  (ack_sync2),
  .Q  (ack_sync3)
  );

  (* shreg_extract = "no", ASYNC_REG = "TRUE" *)
  FD #(
   .INIT (1'b0)
  ) ack_sync_reg4 (
  .C  (drpclk_in),
  .D  (ack_sync3),
  .Q  (ack_sync4)
  );


assign ack_i = ack_sync3 ^ ack_sync4;

assign cpll_reset_i = cpllreset_sync || cpllreset_ovrd_i;


You will also need to update the XDC constraints:   

add the below line to the XDC:

set_false_path -to [get_cells -hierarchical -filter {NAME =~ *ack_sync_reg1}]

To Be Fixed: 2014.3
CR: 793340


AR# 60860
Date Created 05/28/2014
Last Updated 07/17/2014
Status Active
Type Release Notes
Devices
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • More
  • Virtex-7
  • Virtex-7 HT
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IP
  • 7 Series FPGAs Transceivers Wizard