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AR# 60912

Vivado-Synthesis: Verilog parameter overridden within instantiation fails with "ERROR:[Synth 8-3438]"

Description

A Verilog parameter overridden within instantiation fails with the below error:

ERROR:[Synth 8-3438] module 'async_fifo' declared at 'async_fifo.v:4' does not have any parameter 'param_test' used as named parameter override ["FifoBuffer.v":28]


Below is the code where the parameter "param_test" is defined outside the module statement.

-------------------------------------------------
module async_fifo #(
parameter DEVICE = "7SERIES",
...
FIFO_RAM_TYPE = "BLOCK_RAM")
( input [FIFO_WIDTH-1:0] din,
...
output prog_full
);

parameter param_test = 1;
......
endmodule
--------------------------------------------------


The module instantiation is as follows where a value of 2 is passed to the parameter param_test:

async_fifo #(.param_test(2)) buffer_fifo (.din(din), ...... );


Why does this occur?

Solution

This is expected behavior.

This issue is seen when parameters are declared using two styles - within the module statement (e.g. DEVICE in the code above) and outside the module statement (e.g. param_tesst).

As per the Verilog LRM when you use both styles of parameters, the parameters that are declared outside of the module statement become local parameters and hence they cannot be overwritten. 

You can overcome the error by declaring all parameters in one style.

Either put them all in the module statement or move them all outside of the module statement.

Either of the below will work


module async_fifo #(
parameter DEVICE = "7SERIES",
...
FIFO_RAM_TYPE = "BLOCK_RAM",
param_test = 1)
( input [FIFO_WIDTH-1:0] din,
...
output prog_full
);


OR

module async_fifo
( input [FIFO_WIDTH-1:0] din,
...
output prog_full
);
parameter DEVICE = "7SERIES";
...
parameter FIFO_RAM_TYPE = "BLOCK_RAM";
parameter param_test = 1;



AR# 60912
Date Created 06/02/2014
Last Updated 06/06/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite