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AR# 60921

Vivado Synthesis - FIFO_SYNC_MACRO is trimmed by Synthesis

Description

My design has two FIFO_SYNC_MACRO instances declared via the COMPONENT declaration in VHDL.

In Vivado versions prior to 2014.1, both instances are present in the synthesized design.

Starting from 2014.1, one FIFO instance is present, but the other macro instance is being trimmed by Synthesis.

COMPONENT FIFO_SYNC_MACRO
    generic (
......

u_fifo0 : FIFO_SYNC_MACRO
   generic map (
......

u_fifo1 : FIFO_SYNC_MACRO
   generic map (
......

How can I resolve this issue?

Solution

The correct usage for unimacros with VHDL is to put the library unimacro and use clause inside the HDL as in the below example:
 

library unimacro;
use unimacro.vcomponents.all;


 
AR# 60921
Date Created 05/29/2015
Last Updated 10/08/2014
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2