This Answer Record contains child answer records covering various aspects of the Vivado HLS design flow.
The Answer Record explains where to find help with integrating the Vivado HLS output IP into the rest of the system.
Note: This answer record is a part of the Xilinx Solution Center for Vivado HLS (Xilinx Answer 47428), which is available to address all questions related to Vivado HLS.
Whether you are starting a new design or troubleshooting a problem, use the Solution Center for Vivado Synthesis to guide you to the right information.
The output from Vivado HLS can be used as an IP block in either the Vivado Design suite, System Generator for DSP (Vivado and ISE versions) or in Xilinx Platform Studio (XPS).
Only designs targeted for
Zynq and 7-series devices can be used packaged the Vivado flows.
A full explanation of these IP packages can be found in the section "Exporting the RTL" in the Vivado Design Suite User Guide High-Level Synthesis
Although the RTL files are available in the Vivado HLS project directory it is recommended to use one of the packaged IP formats.
If there is a requirement to use only the output RTL files, the files from within the packaged IP directories should be used.
Do not use the HDL files in the project syn, impl/verilog or impl/vhdl folders, as these may not have all required AXI buses interfaces.
Vivado and IP Integrator Flows
A Vivado HLS design can be used in the Vivado Design Suite by creating IP for the IP Catalog. The Vivado QuickTake video Packaging Vivado HLS IP for use from Vivado IP Catalog demonstrates how IP can be exported to the Vivado IP catalog.
The tutorial Using HLS IP in IP Integrator in the Vivado HLS Tutorials
An addition tutorial Using HLS IP in a Zynq Processor Design shows not only how to connect up HLS IP in a Zynq design using IP Integrator, but also how to integrate the IP with the software on the Zynq CPU, process the entire design through the SDK software environment and run the system on a ZC702 board.
The Application note Accelerating OpenCV Applications with Zynq using Vivado HLS Video Libraries (XAPP1167, design files here) explains how a design with OpenCV functions is processed using Vivado and IP Integrator.
System Generator for DSP flows
A Vivado HLS design can be incorporated into System Generator for DSP by creating IP for System Generator (Vivado or ISE).
The Vivado QuickTake videos Generating Vivado HLS block for use in System Generator for DSP and Using Vivado HLS C/C++/System C block in System Generator demonstrate how IP can be exported to System Generator and used.
The tutorial Using HLS IP in System Generator for DSP in the Vivado HLS Tutorial
Application Notes Floating-Point
PID Controller Design with Vivado HLS and System Generator for DSP (XAPP1163) and Implementing Carrier Phase Recovery Loop Using
Vivado HLS (XAPP1173) both provide detailed application examples implemented
using Vivado HLS and System Generator for DSP.
Xilinx Platform Studio (XPS) Flows
The Vivado HLS output can be incorporated into a design in Xilinx Platform Studio by System Generator for DSP by creating the IP in pcore format.
The Vivado QuickTake videos Generating Vivado HLS Pcore for use in Xilinx Platform Studio and Using Vivado HLS C/C++/System C based Pcores in XPS demonstrate how IP can be exported to XPS and used in an ISE flow.
The XPS and ISE flow is used in the Application Notes "Zynq-7000 All Programmable SoC Accelerator for Floating-Point Matrix Multiplication using Vivado HLS" (XAPP1170) and "Zynq Sobel Filter Implementation Using Vivado HLS" (XAPP890) both provide detailed application examples implemented using Vivado HLS, XPS and ISE