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AR# 60951

MIG UltraScale RLDRAM3 and QDRII+ - timing failure from XiPHY to riu_clk


Version Found: v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)

The following path may fail timing for MIG UltraScale RLDRAM3 and QDRII+ designs as a result of a long route delay.

Slack (VIOLATED) :        -0.206ns  (required time - arrival time)
  Source:                 u_SN66_virtexuQDRIIPLUS_vlog_475MHz_vivado/inst/u_qdriip_phy/phycal/phy/byteWrap[1].u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by TX_BIT_CTRL_OUT[26]  {rise@0.000ns fall@2.101ns period=4.202ns})
  Destination:            u_SN66_virtexuQDRIIPLUS_vlog_475MHz_vivado/inst/u_qdriip_phy/phycal/cal/caladdrdecode/riu2clb_rd_data_riu_r_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by riu_clk  {rise@0.000ns fall@4.202ns period=8.404ns})
  Path Group:             riu_clk
  Path Type:              Setup (Max at Slow Process Corner)


If this exact path fails timing please open a  webcase with Xilinx Technical Support.

Revision History:
06/04/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 60951
Date 06/05/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
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