Version Found: RLDRAM3 v5.0 (Rev. 1), QDRII+ v5.0 (Rev .1)
The following path can fail timing for MIG UltraScale RLDRAM3 and QDRII+ designs as a result of a long route delay.
If this exact path fails timing please open a Service Request with Xilinx Technical Support.
06/04/2014 - Initial Release