UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 60953

MIG UltraScale - Output Products must be generated before opening the IP Example Design

Description

Version Found: v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)

Output products must be generated before opening the MIG IP Example Design.

If they are not, the following error can occur:

ERROR: [Vivado 12-172] File or Directory '/scratch/users/avdhesh/testcases/779810/project_1/project_1.srcs/sources_1/ip/mig_0/rtl/controller/mig_v5_0_ddr_mc_wtr.sv' does not exist

    while executing
"add_files -scan_for_includes -fileset [current_fileset -simset] \
  [list [file join $srcIpDir tb/sim_tb_top.sv]] \
  [list [file join $srcIpDir rtl/i..."
    (file "/scratch/users/avdhesh/testcases/779810/project_1/project_1.srcs/sources_1/ip/mig_0/mig_0_ex.tcl" line 47)

Solution

To generate the output products, right click on the MIG XCI file and select "Generate Output Products..."

Revision History:
06/04/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 60953
Date Created 06/04/2014
Last Updated 06/05/2014
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale