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AR# 60967

2014.4 Logic Opt - Mandatory Logic Optimization is transforming two FFs to an IDDR despite constraints


I have an issue in my design where Mandatory Logic Optimization (MLO) is transforming two flip-flops driven by an input path into an IDDR despite DONT_TOUCH and IOB=FALSE constraints.


MLO is run whenever a post-synthesis design is loaded by Vivado, so this can appear to be the synthesis result when it is actually a post-synthesis optimization.

This will be fixed in a future release so that MLO will not do this IDDR optimization when the above constraints are applied.
AR# 60967
Date 01/29/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
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