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AR# 60978

Zynq-7000 SoC - QSPI Controller Reports Wrong “Busy Status” Of Flash Memories In Dual Parallel Configuration When Auto CS And “Divide by 2” Baud Rate Is Used


When the QSPI controller is in dual parallel mode and issues a read status (RDSR) command to external flash memory devices using TXD2, the controller should combine the Write-In-Progress (WIP) bit from both flash devices by OR'ing them and reporting the result as the final status.

However, when the QSPI controller Manual_CS is set to auto mode and BAUD_RATE_DIV is divide by 2, it only reports the status of the lower device.

Therefore, the status is incorrect if the lower memory is ready and upper memory is still busy.

This is a third-party errata; this issue will not be fixed.



Impact:   Major. Under the described condition, the QSPI controller in dual parallel mode can fail an operation on the lower memory when a prior write operation to the lower memory takes longer than the upper memory.

Work-around:           Set Manual_CS to manual mode instead of auto mode or use a BAUD_RATE_DIV other than 2.

Configurations Affected:       All Zynq devices using the QSPI controller in dual parallel mode with the settings listed in the description section.


Device Revision(s) Affected: All, no plan to fix. 

AR# 60978
Date Created 06/04/2014
Last Updated 08/26/2014
Status Active
Type Known Issues
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q