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AR# 60984

2013.4/2014.1/2014.2 Vivado Simulation - PCIE_3_ 1 - VCS VHDL simulation reports Error Type mismatch 'SIM_JTAG_IDCODE' is STD_LOGIC_VECTOR, but formal 'SIM_JTAG_IDCODE' is INTEGER

Description

When using VCS to simulate PCIE 3_1 generated in the Vivado IP catalog, the following error can occur:

Error-[OVA1ACTUALTYPEMISMATCH_COMPONENT_ENTITY] Type mismatch
 
$XILINX_VIVADO/data/vhdl/src/unisims/secureip/PCIE_3_1.vhd, 1312
 
SIP_PCIE_3_1
 
  Line 1.794:
 
  Please generate .lis file by 'vhdlan -list ...' and see details.
 
 --+       GSR => GSR)
 
  Actual 'SIM_JTAG_IDCODE' is STD_LOGIC_VECTOR, but formal 'SIM_JTAG_IDCODE'  is INTEGER when binding component
 

  'SIP_PCIE_3_1'($XILINX_VIVADO/data/vhdl/src/unisims/secureip/PCIE_3_1.vhd:1310)

  to entity

  'SIP_PCIE_3_1'($XILINX_VIVADO/data/secureip/pcie_3_1/pcie_3_1_001.vp:16).Instance
 
  label is
 
  'PCIE_3_1_INST'($XILINX_VIVADO/data/vhdl/src/unisims/secureip/PCIE_3_1.vhd:6835).

Solution

This issue is fixed in Vivado 2014.3. 

Workaround:

1. Use VCS version I-2014.03.

2. Open the file PCIE_3_1.vhd from the location: $XILINX_VIVADO\data\vhdl\src\unisims\secureip and go to line 576.

SIM_JTAG_IDCODE : std_logic_vector(31 downto 0) := X"00000000";

3. Change the below declaration:

SIM_JTAG_IDCODE : std_logic_vector(31 downto 0) := X"00000000";

to

SIM_JTAG_IDCODE : bit_vector(31 downto 0) := X"00000000";


4. Save the file and re-run simulation.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58895 Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries - UNISIM & SIMPRIM N/A N/A
AR# 60984
Date Created 06/05/2014
Last Updated 04/09/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
IP
  • 7 Series Integrated Block for PCI Express (PCIe)