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AR# 61002

2014.2 Vivado IP Flows - A user IP GUI in IP Packager shows a paremeter value set to '0' when paramter is derived by other parameters in verilog code


When using Create and Package IP, IP Packager will visually show a value of  '0' for a parameter that has been derived using different parameters in the Verilog source file.

For example: This issue is seen using axi_master.v to create and package IP.

The Verilog file has the below parameter syntax which shows the value in the customization GUI to be 0 .

However the actual value used to work out the interfaces is correct as can be seen in project_1 in which I have generated the IP.
parameter integer  C_BURST_LEN        = 16,

parameter integer  C_M_AXI_DATA_WIDTH       = C_BURST_LEN*4
Looking in the axi_master.v file it can be seen that M_AXI_WDATA and M_AXI_WSTRB use C_M_AXI_DATA_WIDTH.

// Master Interface Write Data

output wire [C_M_AXI_DATA_WIDTH-1:0]      M_AXI_WDATA,

output wire [C_M_AXI_DATA_WIDTH/8-1:0]    M_AXI_WSTRB,

 The value of M_AXI_WDATA and M_AXI_WSTRB are shown as 0 in the customization GUI.


This is a visual bug in the GUI and the correct values are calculated in the source files.

Although the value in the GUI is 0, the actually value used to work out the interfaces is correct as can be seen in a project that uses the IP.
For the example above, when the core is added to a project you can see that the correct values are calculated as below.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] M_AXI_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] M_AXI_WSTRB;
AR# 61002
Date Created 06/05/2014
Last Updated 06/20/2014
Status Active
Type Known Issues
  • SoC
  • FPGA Device Families
  • Vivado Design Suite - 2014.1