We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61018

Vivado Synthesis - Logics inserted between registers marked with ASYNC_REG


For registers with ASYNC_REG attributes, no optimizations should be done that might insert additional logic into the data path or increase the fanout of the associated registers.

However, in some cases logics can be inserted between registers with ASYNC_REG attributes. 


This is unexpected behavior and has been fixed in Vivado 2015.1.

To work around this issue, add a dont_touch attribute on the net between the two registers.
AR# 61018
Date Created 06/05/2014
Last Updated 04/07/2015
Status Active
Type Known Issues
  • Vivado Design Suite