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AR# 61035

FIFO Generator v12.0 - What is the correct flow to simulate the core in ModelSim Standalone?

Description

When I simulate the FIFO Generator behavioral model in ModelSim, I receive the following errors:

vcom /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd
# Model Technology ModelSim SE-64 vcom 10.2a Compiler 2013.03 Mar 15 2013
# -- Loading package STANDARD
# ** Error: /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd(46)): in protected region.
# ** Error: /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd(46)): in protected region.
# ** Error: /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd(46)): in protected region.
# ** Error: /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd(46)): in protected region.
# /tools/gensys/modelsim/10.2a/linux_x86_64/vcom failed.

 

How can I simulate the FIFO Generator in standalone mode?

Solution

The FIFO Generator behavioral model in Vivado expects a library called fifo_generator_12_0 and a list of submodules.

You will need to add the following lines to the wrapper RTL code and testbench :

LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;


Below is a full compile list to simulate the FIFO Generator v12.1 core:

vlib msim/fifo_generator_v12_0

vmap fifo_generator_v12_0 msim/fifo_generator_v12_0

vcom -work fifo_generator_v12_0 /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd

vcom -work fifo_generator_v12_0 /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/fifo_generator_v12_0_pkg.vhd
vcom -work fifo_generator_v12_0 /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/common/input_blk.vhd
vcom -work fifo_generator_v12_0 /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/common/output_blk.vhd
vcom -work fifo_generator_v12_0 /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/common/shft_wrapper.vhd
vcom -work fifo_generator_v12_0 /proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/common/shft_ram.vhd
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/common/wr_pf_as.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/common/wr_pf_ss.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/common/rd_pe_as.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/common/rd_pe_ss.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/delay.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/bin_cntr.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/clk_x_pntrs_builtin.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/logic_builtin.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/builtin_prim.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/builtin_extdepth.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/builtin_top.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/reset_builtin.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/builtin_prim_v6.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/builtin_extdepth_v6.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/builtin_extdepth_low_latency.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/builtin_top_v6.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/builtin/fifo_generator_v12_0_builtin.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/ramfifo/bram_sync_reg.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/ramfifo/bram_fifo_rstlogic.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/ramfifo/reset_blk_ramfifo.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/ramfifo/axi_reg_slice.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/fifo_generator_top_bi_sim.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/fifo_generator_v12_0_synth.vhd"
vcom  -work fifo_generator_v12_0 -93 "/proj/gsd/vivado/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/hdl/fifo_generator_v12_0_top.vhd"

AR# 61035
Date Created 06/06/2014
Last Updated 01/05/2015
Status Active
Type General Article
IP
  • FIFO Generator