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AR# 61112

MIG 7-Series - How to constrain sys_rst


When the sys_rst signal is driven from an internal register within the user design and is run on a clock that is related to the clk_ref, it can be difficult or impossible to meet timing.  

Is the failing path on the FDPE "PRE" pin for sys_rst (see below figure) a true violation?



Sys_rst is a fully asynchronous reset pin.

Inside the MIG core, the reset is synchronized to the internal clk_ref to create a synchronous reset.

Therefore, it is asserted asynchronously and deasserted synchronously.


Because of this design, it is perfectly safe to put a set_false_path constraint on the sys_rst pin.

AR# 61112
Date Created 05/29/2015
Last Updated 09/22/2014
Status Active
Type General Article
  • MIG 7 Series