UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61114

MIG Ultrascale DDR4/DDR3 - Why can't pins N1 and N12 be used as data (DQ) pins?

Description

The following pin-out rule is included in the PG150 DDR4 and DDR3 Pin and Bank Rules sections:


dqs, dq, and dm location.


a. Designs using x8 or x16 components dqs must be located on a dedicated byte clock pair in the upper nibble designated with U. dq associated with a dqs must be in the same byte lane on any of the other pins except pins 1 and 12.
b. Designs using x4 components dqs must be located on a dedicated byte clock pair in the nibble. dq associated with a dqs must be in the same nibble on any of the other pins except pins N1 (lower nibble) and pin N12 (upper nibble).

What is the restriction on pins 1 (N1) and 12 (N12)?

Solution

The XiPHY block includes specific clock routing to each of the I/O elements within the byte group.  

Pins N1 and N12 do not have the required clock routing to be used as data (DQ) pins.  

Calibration cannot be completed on the clock routing to the N1 and N12 pins.  

Therefore, it is not possible architecturally for either N1 or N12 to be used as data pins.

AR# 61114
Date Created 06/12/2014
Last Updated 06/23/2014
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale