UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61161

V3.1 - 7 Series FPGAs Transceivers Wizard - An incorrect GTREFCLK port name may be generated in an example design

Description

The below error message will be reported when an incorrect GTREFCLK port name is generated in an example design by the Transceiver Wizard:

[Synth 8-448] named port connection 'Q10_CLK_GTREFCLK_PAD_N_IN' does not exist for instance 'gt_usrclk_source' of module 'gtwizard_0_GT_USRCLK_SOURCE' ["c:/Work/Case/2014/201403/1002971/GTH_1140T/project_3/gtwizard_0_example/gtwizard_0_example.srcs/sources_1/imports/example_design/support/gtwizard_0_support.v":1645]

Solution

The workaround is to manually modify the port in the files <component_name>_support.v/<component_name>_.v and <component_name>_gt_usrclk_source.v[hd]

This should be changed based on the reference clock selection

from
Q10_CLK_GTREFCLK_PAD_N_IN/q10_clk_gtrefclk_pad_n_in

to
Q10_CLK1(or 0)_GTREFCLK_PAD_N_IN/q10_clk1( or 0)_gtrefclk_pad_n_in 

This issue is scheduled to be fixed in the 2014.3 release.
AR# 61161
Date Created 06/17/2014
Last Updated 06/24/2014
Status Active
Type General Article
Devices
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2