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AR# 61174

MIG 2.0 - Failing timing in the MIG when implementing my complete Block Design, why?


Version Found: MIG 7 Series v2.0 Rev 2 (Vivado 2014.1)

When running implementation for IPI designs which contain the MIG 7 Series v2.0 IP core within the block design, timing violations sometimes occur in the MIG core.

These timing failures do not occur in the example design for the same configuration of the MIG.

Why does this happen? Is this a known issue?


This issue can occur in cases where Vivado Synthesis is adding additional logic levels to some paths in the MIG IP core when it is part of an IPI block design. 

This additional logic and the resulting routing delays between these logic cells lead to substantial additional delay on these paths and ultimately results in these paths now failing timing.

These additional logic levels do not occur when the MIG core is synthesized out of the block design or synthesized in OOC mode.

However, OOC mode is not supported for IP contained within a block design. 

A CR has been filed against this issue and is under investigation for a solution in the future. 

This can also be seen in Vivado 2014.2.

Please contact Xilinx Tech Support for further assistance with this issue.

AR# 61174
Date Created 06/18/2014
Last Updated 09/05/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
  • Memory Interface Generator (MIG)