This issue can occur in cases where Vivado Synthesis is adding additional logic levels to some paths in the MIG IP core when it is part of an IPI block design.
This additional logic and the resulting routing delays between these logic cells lead to substantial additional delay on these paths and ultimately results in these paths now failing timing.
These additional logic levels do not occur when the MIG core is synthesized out of the block design or synthesized in OOC mode.
However, OOC mode is not supported for IP contained within a block design.
A CR has been filed against this issue and is under investigation for a solution in the future.
This can also be seen in Vivado 2014.2.
Please contact Xilinx Tech Support for further assistance with this issue.