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AR# 61181

2014.2 Vivado IP Flows - Selecting "Create HDL Wrapper" for a block design gives "bad lexical cast: source type value could not be interpreted as target"


I have created a block design (BD) in IP Integrator (IPI). 

When I right click on the BD icon to select "Create HDL wrapper" or "Generate  Target" Vivado returns the below error. 

bad lexical cast: source type value could not be interpreted as target



This error has been seen in the following situations.

  • When an Aurora 64B66B IP core is used in a block design and some of the clock-ports are specifying their FREQ_HZ as double (for example sync_clk and user_clk). 
    While writing the OOC XDC file during HDL generation, Vivado is doing a bad lexical cast while interpreting this data.
  • In cases where the AXI Ethernet and AXI 10G Ethernet have not specified CONFIG.FREQ_HZ and CONFIG.PHASE parameters for their clock-output pins in 2014.2.
    The bad lexical_cast problem will happen during post parameter-propagation DRC checks (validate_bd_design)  when running clock-reset synchronization DRC.
    This happens because the clock output ports frequency could not be found by looking only at hierarchy boundary.
    Vivado runs parameter propagation during "generate_target" and "Create HDL wrapper" so the error will occur when running these tasks as well.


This issue will be fixed in Vivado release 2014.3.

A patch has been created to resolve this error in Vivado 2014.2. 

To install this patch download the attached zip file for the desired operating system and follow the instructions provided in the readme file contained in the archive.

Windows: ar61181_Vivado_2014_2_Win_preliminary_rev2.zip

Linux: ar61181_Vivado_2014_2_Lin_preliminary_rev2.zip


Associated Attachments

AR# 61181
Date Created 06/18/2014
Last Updated 07/30/2014
Status Active
Type Known Issues
  • FPGA Device Families
  • Vivado Design Suite - 2014.2