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AR# 6121

1.5 NGD2VER/NGD2VHDL: WARNING:baspp - hierarchical block"" has been flattened. Its pins will not be observable in the generated simulation model.


Keywords: Ngd2ver, Ngd2vhdl, ngdanno, -r, retain hierarchy

Urgency: Standard

General Description:
What are some reasons why Ngd2ver/Ngd2vhdl will not retain
hierarchy even though the "-r" switch is specified?

This is the generic warning that NGD2VER/NGD2VHDL outputs:

WARNING:baspp - hierarchical block "" has been flattened.
Its pins will not be observable in the generated simulation model.



Ngdanno was run without the ngm file.


NGDANNO could not construct a simulation model of the logical reference
(user's design) vs. the physical reference (FPGA architecture). Basically,
the simulation netlist is written in terms of gates rather than FPGA
architectural components. So to facilitate modeling, the hierarchy was

Since the problem is related to Ngdanno's inability to distribute physical
delays onto logical elements, Ngdanno replaces the logical elements with
a functionally equivalent physical model with correct delays. If the logical
elements for any given CLB span hierarchy, that hierarchy is flattened
during this substitution process.

In short, ngd_prep (this is called during Ngd2vhdl/Ngd2ver processing)
has to flatten hierarchy if it does a physical to logical substitution. The
substitution occurs because Ngdanno fails to generate delays on part of
the user's logical design.

The "part of the design" are those pieces which were mapped and packed
into a physical component (CLB, IOB, etc). For the sake of this argument,
this "part" will be referred to as the "sub-circuit." The sub-circuit must be
removed and the physical model then inserted into the user's original design
at a singular level in the user's design hierarchy. It is this singularity that
requires ngd_prep to flatten the user's levels of hierarchy. Thus, flattening
occurs when any of the elements in the sub-circuit exist on different levels
of the hierarchy.

For example, assume the following is the user's sub-circuit which was
packed into a CLB. Assume that this sub-circuit is buried in some part of
the user's hierarchy:

 Logical Design with Hierarchy
Logical Design with Hierarchy

Now if both AND2 and DFF get packed into a component of type CLB and
Ngdanno failed to generate a logical back-annotation for the circuit, then
it is necessary for Ngd_prep to substitute the physical model back into the
logical implementation of this design. The physical model in this case is:

 Physical Model
Physical Model

Since the physical model must be instantiated as a whole (not in part), it is
necessary for the Ngd_prep to remove the hierarchical blocks USERBLK1
and USERBLK2 (in the first figure). When Ngd_prep does this, it explicitly
informs the user that it is flattening the hierarchical blocks. In this case, the
user would lose hierarchical blocks USERBLK1 and USERBLK2.

The following is the resulting implementation where the physical model has
replaced the user's sub-circuit.

 Physical Model with Flattened Hierarchy
Physical Model with Flattened Hierarchy
AR# 6121
Date 08/22/2001
Status Archive
Type ??????
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