When an Aurora 64B66B/Aurora 8B10B design is created with CPLL configuration, the INIT_CLK frequency can be any value between 6.25Mhz to line_rate/64 or 200Mhz for Aurora 64b66b or line_rate/<internal datapath width> or 200Mhz for Aurora 8b10b, whichever is lower.
If the INIT_CLK frequency is chosen as anything outside of the above determined values, lane_up/channel_up are not asserted high on the board.
To resolve this issue, update the C_FREERUN_FREQUENCY parameter with the exact
frequency in the
inside the IP folder.