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AR# 61293

HMC 100G bandwidth demo

Description

This reference design showcases over 100G independent read and write throughput interfacing with Micron HMC memories. it utilizes 16 GTs running at 12.5G each with a 200G raw throughput and 120G usable bandwidth.

The Ethernet packet generation and checking are part of this design.

Attachments

Associated Attachments

Name File Size File Type
HMC_TM_Demo_MW.zip 3 MB ZIP
AR# 61293
Date Created 06/26/2014
Last Updated 11/23/2016
Status Active
Type General Article
Devices
  • Virtex-7 HT
Tools
  • Vivado Design Suite - 2013.4
IP
  • Memory Interface and Storage Element