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AR# 61302

Aurora 8B10B v10.0 - Channel up is not asserted with some configurations

Description

With Aurora 8B10B v10.0, Channel up is not asserted with some configurations. 

However, Lane up is asserted. 

This answer record provides the fix for this issue.

Solution

This issue occurs when "tx_lock" is not used in the SYSTEM_RESET equation in  the <component_name>_RESET_LOGIC module. 

Please ensure that the TX_LOCK_IN is synchronized to the USER_CLK domain and used in the SYSTEM_RESET equation as shown in the logic below:

 

tx_lock_cdc_sync : <component_name>_cdc_sync
      generic map
        (
           c_cdc_type      => 1             ,  
           c_flop_input    => 0             , 
           c_reset_state   => 0             , 
           c_single_bit    => 1             , 
           c_vector_width  => 2             , 
           c_mtbf_stages   => 3               
         )
      port map
         (
           prmry_aclk      => INIT_CLK_IN         ,
           prmry_resetn     => '1'                ,
           prmry_in        => TX_LOCK_IN          ,
           prmry_vect_in   => "00"                ,
           scndry_aclk     => USER_CLK            ,
           scndry_resetn    => '1'                ,
           prmry_ack       => open                ,
           scndry_out      => tx_lock_sync        ,
           scndry_vect_out => open                    
          );

assign SYSTEM_RESET = RESET || !gt_txresetdone_r3 || !gt_rxresetdone_r3 || link_reset_sync || !tx_lock_sync;


Revision History:

08/04/2014 - Initial Release

AR# 61302
Date Created 06/27/2014
Last Updated 08/06/2014
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.3
IP
  • Aurora 8B/10B