For full details on the clocking structure requirements and sharing of the Input Clock Source (sys_clk_p), please refer to the "Clocking" sections of (PG150) LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions.
Note: MIG's MMCM cannot be driven by another MMCM/PLL (Cascaded MMCMs).
It must be driven directly by GCIO or using a BUFG on the CLOCK_DEDICATED_ROUTE=BACKBONE route.
For guidelines on using differential inputs LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (i.e. 1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs) refer to the "LVDS and LVDS_25 (Low Voltage Differential Signal)" section in the (UG571) UltraScale SelectIO Resources User Guide.
For information on how to manually modify IP cores in Vivado, see (Xilinx Answer 57546).