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AR# 61304

MIG UltraScale - Clocking Guidelines and Requirements


The MIG UltraScale IP has a very specific clocking architecture and system input clock requirements that must be followed when using the IP to minimize clock jitter and to ensure that the proper clock frequencies and phase shifts are set up for proper operation of the memory interface.

The generated core follows all clocking guidelines and implements the required clocking structure.

This answer record includes information on the system input clock that is provided as an input to the MIG UltraScale IP core.


For full details on the clocking structure requirements and sharing of the Input Clock Source (sys_clk_p), please refer to the "Clocking" sections of (PG150) LogiCORE IP UltraScale Architecture-Based FPGAs Memory Interface Solutions.

Note: MIG's MMCM cannot be driven by another MMCM/PLL (Cascaded MMCMs).

It must be driven directly by GCIO or using a BUFG on the CLOCK_DEDICATED_ROUTE=BACKBONE route.

For guidelines on using differential inputs LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (i.e. 1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs) refer to the "LVDS and LVDS_25 (Low Voltage Differential Signal)" section in the (UG571) UltraScale SelectIO Resources User Guide.

For information on how to manually modify IP cores in Vivado, see (Xilinx Answer 57546).

Revision History:
05/26/2015 - Updated to include no cascading of MMCM's allowed
04/01/2015 - Updated to reflect new clocking guidelines in 2015.1
10/10/2014 - Updated differential I/O standard section
08/04/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 61304
Date 06/09/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale