When implementing a design using partial reconfiguration, I see the following error:
How can this be resolved?
This is a known issue where no PPLOC is assigned because the net in question has a ROUTE_STATUS of INTRASITE.
This has been fixed in the Vivado 2014.3 release.
Initially, logic within an RM has a looping connection as seen in the image below.
During place_design, a mandatory LUT1 is inserted on the boundary net.
However, this LUT1 is incorrectly placed in the same SLICE site as the FF that it drives.
This placement makes the net INTRASITE and does not allow for the PPLOC to be assigned or the net routed.
To work around this in 2014.1, separate the LUT1 and FF to different SLICE sites.
Because the LUT1 is added during place_design, the logic will first have to be un-placed, moved, and then re-placed.
This can be done with only the affected logic, or by un-placing and re-placing the entire design as shown below: