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AR# 61354

2014.4 Vivado Partial Reconfiguration - PPLOC not set when logic of boundary net is in the same SLICE


When implementing a design using partial reconfiguration, I see the following error:

ERROR: [Constraints 18-1026] HDPostRouteDRC-02: the boundary net mnt_voq_i_inst/vcm_inst/HD_PR_CommonDriver_InsertedNet_mnt_voq_i_inst_vcm_inst_cpm_o_69_ connecting to the port cpm_i[69] of reconfigurable cell mnt_voq_i_inst/vcm_inst does not have PPLOC on it. The issue might be caused by un-routed boundary net. For detailed routing information, please use TCL command 'report_route_status'.

How can this be resolved?


This is a known issue where no PPLOC is assigned because the net in question has a ROUTE_STATUS of INTRASITE. 

This has been fixed in the Vivado 2014.3 release.

Initially, logic within an RM has a looping connection as seen in the image below.


During place_design, a mandatory LUT1 is inserted on the boundary net. 

However, this LUT1 is incorrectly placed in the same SLICE site as the FF that it drives. 

This placement makes the net INTRASITE and does not allow for the PPLOC to be assigned or the net routed. 

To work around this in 2014.1, separate the LUT1 and FF to different SLICE sites. 

Because the LUT1 is added during place_design, the logic will first have to be un-placed, moved, and then re-placed. 

This can be done with only the affected logic, or by un-placing and re-placing the entire design as shown below:

open_checkpoint mantis_i_top_placed.dcp
place_design -unplace
set_property LOC SLICE_X265Y337 [get_cells mnt_voq_i_inst/vcm_inst/HD_PR_CommonDriver_InsertedInst_mnt_voq_i_inst_vcm_inst_cpm_o_69_]
set_property LOC SLICE_X266Y337 [get_cells mnt_voq_i_inst/vcm_inst/ff_cpm_i/q0[69]]
set my_cells [get_cells [list mnt_voq_i_inst/vcm_inst/HD_PR_CommonDriver_InsertedInst_mnt_voq_i_inst_vcm_inst_cpm_o_69_ mnt_voq_i_inst/vcm_inst/ff_cpm_i/q0[69]]]
place_design -cells $my_cells
AR# 61354
Date 04/02/2015
Status Archive
Type General Article
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
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