Version Found: MIG v6.0
Version Resolved: See (Xilinx Answer 58435)
MIG UltraScale currently does not deliver a PHY-Only solution where the controller and user interface are removed, allowing users to integrate custom controllers.
This support will be provided through the MIG GUI starting with Vivado 2014.4.
When using MIG v6.0 available with Vivado 2014.3, this Answer Record can be followed to manually create a PHY only solution.
The Answer Record provides manual steps to modify the full MIG UltraScale DDR4/3 IP to remove the controller and user interface leaving only the PHY and calibration logic.
1. Create the MIG IP in Vivado for the required configuration.
2. Generate all targets but turn-off OOC while generating.
This will generate all the required files (RTL, others) but not run synthesis to generate a DCP for the IP.
3. Next a set of RTL files need to be updated/added/removed.
To make rtl edits, please use an external editor. Vivado will not allow files to be edited.
4. In the generated design, edit the mig_v5_0_ddr4_mem_intfc.sv file to remove the memory controller (mc) and user interface (UI): (please refer to attached file for an example)
5. In the generated design, edit the mig_0_mig.sv file: (please refer to attached as an example)
6. Edit the mig_0.sv file: (please refer to attached as an example)
7. After modifying the files, do not re-customize MIG. If MIG is re-customized, all of the updated files in the above steps will be over-written.
8. Add a top level wrapper. You can use the attached example_top.sv and example_tb_phy.sv files as an example.
9. After making these changes, the design hierarchy should look like the following:
10. A top-level constraint file is needed to provide physical location constraints for the DDR interface and other diagnostic signals need to be provided.
11. Run synthesis, implementation and generate bitstream
Note: There may be a Critical Warning related to pblock constraint which can be ignored.
Below is an example: