We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61438

2014.2 - Synthesis : Limitations seen with 3-state I/O buffer inference from IPI flow


The below piece of HDL code infers a 3-state I/O buffer with a OBUFT and IBUF for bidirectional configuration in Vivado synthesis.

However, when this code is brought into the IPI flow as part of an IP using IP Packager, VSS does not infer the desired 3-state I/O.

Why does this happens and how can it be resolved?

3-state I/O HDL:

The architecture rtl of iobuf is
     IO <= I when T = '0' else 'Z';
     O <= IO;
end rtl;

Correct synthesis of the code:
Incorrect synthesis of the code using IPI flow:


This difference in the synthesized design is due to the addition of the DONT_TOUCH attribute in the signals/entity of the 3-state I/O buffer.

Since 2014.2, this attribute has become more restrictive and preserves HDL code as it is defined.

The attribute is applied in the IPI flow by Vivado via a file called "dont_touch.xdc", the purpose of which is to preserve all of the pins from the BD design.

This can be observed at the beginning of the Synthesis.rpt file.


To avoid the incorrect inference of logic from Vivado you can instantiate the OBUFT + IBUF directly.

An iobuf.vhd file is attached to this answer record.


Associated Attachments

Name File Size File Type
iobuf.vhd 1 KB VHD
AR# 61438
Date Created 07/10/2014
Last Updated 09/05/2014
Status Active
Type Known Issues
  • FPGA Device Families
  • Vivado Design Suite - 2014.2