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AR# 61442

Vivado - VHDL Record type not supported with Out-of-Context flow


Ports defined as a Record type used in a module which is synthesized as out-of-context may generate an error during the Synthesis stage.


This problem occurs because the netlist generated from the OOC flow will not match the ports defined in the top module.

Those port names will contain some square brackets with the sub_name of the signals defined in the Record type similar the following:

Record type definition:

type type_rec_stat is record
cat_build : std_logic_vector (31 DOWNTO 0);
dog_build : std_logic_vector (31 DOWNTO 0);
end record type_rec_stat 

The netlist names will be similar to the following:

REC_STAT[cat_build] : out std_logic_vector (31 DOWNTO 0);

A work-around is to modify the netlist name as follows:

\REC_STAT[cat_build]\ : out std_logic_vector (31 DOWNTO 0);
\REC_STAT[dog_build]\ : out std_logic_vector (31 DOWNTO 0);

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Associated Answer Records

AR# 61442
Date 12/10/2014
Status Active
Type Known Issues
  • FPGA Device Families
  • Vivado Design Suite
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