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AR# 61446

2014.2 Vivado - When I open a synthesized design I get: "ERROR: [Common 17-48] File not found: .../my_proj.data/ddr2_IP/ports.xml"


I have synthesized part of my design as an Out of context (OOC) design.  

When I open this OOC synth run, I receive the errors below:

ERROR: [Common 17-48] File not found: /proj/my_proj/my_proj.data/ddr2_IP/ports.xml
ERROR: [Common 17-48] File not found: /proj/my_proj/my_proj.data/ddr2_IP/chipscope.xml


This problem is solved in Vivado 2014.3.

To work around this issue in earlier versions, use the following command:

remove_files <files.xml>

AR# 61446
Date Created 07/10/2014
Last Updated 12/16/2014
Status Active
Type Known Issues
  • FPGA Device Families
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2014.2