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AR# 61491

AXI Bridge for PCI Express v2.4 - Example design simulation of the core configured for link width greater than x1 always trains down to x1 in some configurations

Description

Version Found: v2.4
Version Resolved and other known issues: (Xilinx Answer 54646)

When generating the AXI Bridge for PCI Express v2.4 core for link width greater than x1, the example design simulation, in some configurations, always trains down to x1.  

Solution

This is a known issue and will be fixed in a future release of the core. 

To work around this issue, make the following modification in the pcie_7x_0_core_top.v file of the root port if the issue is encountered.

- parameter LTSSM_MAX_LINK_WIDTH to 4

- parameter USER_CLK_FREQ to 2    (for x4 GEN1)
                      USER_CLK_FREQ to 3    (for x4 GEN2)

Note: "Version Found" refers to the version where the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
15/07/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54646 AXI Bridge for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 61491
Date Created 07/14/2014
Last Updated 07/14/2014
Status Active
Type Known Issues
IP
  • AXI PCI Express (PCIe)