This is a known issue and will be fixed in a future release of the core.
To work around this issue, make the following modification in the pcie_7x_0_core_top.v file of the root port if the issue is encountered.
- parameter LTSSM_MAX_LINK_WIDTH to 4
- parameter USER_CLK_FREQ to 2 (for x4 GEN1)
USER_CLK_FREQ to 3 (for x4 GEN2)
Note: "Version Found" refers to the version where the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
15/07/2014 - Initial Release