UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61548

Vivado Sysgen - When Logical block has output set to Boolean and "ERROR: [Synth 8-944] 0 definitions of operator "/=" match here" may occur

Description

When I try to generate the Synthesized Checkpoint from the Vivado Sysgen Token or when Synthesizing the generated HDL Netlist or IP Catalog output from Sysgen I receive the following error:

ERROR: [Synth 8-944] 0 definitions of operator "/=" match here [F:/<path_to_test_model>/export_cast/Synthesized Checkpoint/logical_bool.srcs/sources_1/imports/sysgen/logical_bool_entity_declarations.vhd:62]

 
The line of code referred to is part of the Logical block code generated from Sysgen.
 

  unregy_3_1_convert <= (fully_2_1_bit /= "0");


Is this a known issue?

Is there any workaround?

Solution

This is a known issue and occurs when the Logical block has its output set to Boolean and the Sysgen language is set to VHDL.

There are two work-arounds at this time:

  1. Set the Sysgen language to Verilog.
  2. Change the output of the Logical block to UFIX_1_0 and then add the Convert block after the Logical block to change this UFIX_1_0 signal to a Boolean.


A request has been filed for this issue to be fixed in the next release.


AR# 61548
Date Created 07/18/2014
Last Updated 07/21/2014
Status Active
Type General Article
Tools
  • Vivado Design Suite
  • Vivado Design Suite - 2014.2
  • System Generator for DSP
  • More
  • Vivado Design Suite - 2013.3
  • Vivado Design Suite - 2013.4
  • Vivado Design Suite - 2014.1
  • Less