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AR# 61550

Vivado IP Integrator - Zync Processor DDR interface is missing some constraints for DDR_ck_n and DDR_ck_p IO ports

Description

After running implementation for my Block Design (BD) which contains the Zync Processing System with DDR3L interface enabled, I notice that the DDR_ck_n and DDR_ck_p IO ports do not have the correct IOSTANDARD applied.

They default to LVCMOS18 which is not correct for a DDR3L (low power DDR3).

Is this a known issue or expected behavior?

Solution

This is a known issue which is present in Vivado 2014.2.

To work around this problem, please manually constrain the IOSTANDARD in your project XDC file as follows:

set_property IOSTANDARD DIFF_SSTL135 [get_ports DDR_ck_n]
set_property IOSTANDARD DIFF_SSTL135 [get_ports DDR_ck_p]

This issue is fixed starting in Vivado 2014.3.

AR# 61550
Date Created 07/18/2014
Last Updated 03/16/2015
Status Active
Type General Article
IP
  • MIG 7 Series
  • MIG