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AR# 61555

MIG UltraScale QDRII+ - multi-driver issue in Cypress memory model causes data errors in simulation


Version Found: v5.0 Rev1
Version Resolved: See (Xilinx Answer 58435)

Cypress QDRII+ memory models give erroneous data errors as a result of the data_out output being driven by two drivers.

The simulation can also fail as a result of the memory model not returning data edge aligned with the CQ/CQ# clock to emulate noise.

Since MIG UltraScale doesn't support full calibration during behavioral simulations the misaligned data and clock will not be aligned properly and may still cause data failures.


To work around the issue ensure the driving events do not occur at the same time and also that the data is received edge aligned with the clock.

This can be done by changing the "tcqd" parameter in the Verilog memory model from #0.15 to #0.0.

For example:

`define tcqd #0.15

`define tcqd #0.0


For more information contact Cypress directly or refer to the Cypress Knowledge Base Article on this topic:


Revision History:

07/20/2014 - Initial Release
AR# 61555
Date 07/24/2014
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale