UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61567

Vivado HLS 2014.2: mapping C function input array to AXI4 lite bus example.

Description

Using Vivado HLS 2014.2, how can an input array from the top level C function be mapped to the AXI4 lite slave bus?

Solution

The directives that need to be used are shown below as pragma with the example array definition in the top level:

void mytop(..., mydatatype myarray[MYWIDTH], ...)

#pragma HLS RESOURCE variable=myarray core=RAM_1P_BRAM metadata="-bus_bundle BUS_CTRL"
#pragma HLS INTERFACE ap_memory port=myarray

Note: Because the array is passed at the top level, the array must be initialized from the outside of the IP as happens here.

In practice this in the C TB or embedded processor C code.

This feature is not supported by the new "native AXI interface" directives that have been introduced with Vivado HLS 2014.1/.2, however this feature will be supported in a future release.

In the meantime, the other directives need to use the same style:

#pragma HLS RESOURCE variable=return core=AXI4LiteS metadata="-bus_bundle BUS_CTRL"

 

With the attached example, rerun from the Vivado HLS command prompt with the command
vivado_hls -f run_hls.tcl
 
After successful completion check the driver file in "proj_top_kintex7/solution1/impl/ip/drivers/top_top_v1_0/src/xtop_hw.h"
 
This is referenced here:
 
// BUS_CTRL
// 0x0000 : Control signals
//          bit 0  - ap_start (Read/Write/COH)
//          bit 1  - ap_done (Read/COR)
//          bit 2  - ap_idle (Read)
//          bit 3  - ap_ready (Read)
//          bit 7  - auto_restart (Read/Write)
//          others - reserved
// 0x0004 : Global Interrupt Enable Register
//          bit 0  - Global Interrupt Enable (Read/Write)
//          others - reserved
// 0x0008 : IP Interrupt Enable Register (Read/Write)
//          bit 0  - Channel 0 (ap_done)
//          bit 1  - Channel 1 (ap_ready)
//          others - reserved
// 0x000c : IP Interrupt Status Register (Read/TOW)
//          bit 0  - Channel 0 (ap_done)
//          bit 1  - Channel 1 (ap_ready)
//          others - reserved
// 0x0010 : reserved
// 0x0014 : Data signal of address
//          bit 31~0 - address[31:0] (Read/Write)
// 0x0018 : reserved
// 0x001c : Data signal of addend
//          bit 31~0 - addend[31:0] (Read/Write)
// 0x1000 ~
// 0x1fff : Memory 'gain' (1024 * 32b)
//          Word n : bit [31:0] - gain[n]
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
#define XTOP_BUS_CTRL_ADDR_AP_CTRL      0x0000
#define XTOP_BUS_CTRL_ADDR_GIE          0x0004
#define XTOP_BUS_CTRL_ADDR_IER          0x0008
#define XTOP_BUS_CTRL_ADDR_ISR          0x000c
#define XTOP_BUS_CTRL_ADDR_ADDRESS_DATA 0x0014
#define XTOP_BUS_CTRL_BITS_ADDRESS_DATA 32
#define XTOP_BUS_CTRL_ADDR_ADDEND_DATA  0x001c
#define XTOP_BUS_CTRL_BITS_ADDEND_DATA  32
#define XTOP_BUS_CTRL_ADDR_GAIN_BASE    0x1000
#define XTOP_BUS_CTRL_ADDR_GAIN_HIGH    0x1fff
#define XTOP_BUS_CTRL_WIDTH_GAIN        32
#define XTOP_BUS_CTRL_DEPTH_GAIN        1024

Attachments

Associated Attachments

Name File Size File Type
AR61567_v1_old_interface.zip 2 KB ZIP
AR# 61567
Date Created 07/21/2014
Last Updated 07/25/2014
Status Active
Type Solution Center
Tools
  • Vivado Design Suite
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2